Digital & Chip Design (HDL / VLSI)

Digital design end to end: Verilog/VHDL, FSMs, pipelining, the RTL-to-GDSII flow and CMOS/VLSI, with C++ foundations and the career layer. A standout differentiator.

All four courses are $240 together, $60 less than buying them one by one.

What is inside

Recommended path

Digital logic & HDL → VLSI & the ASIC flow → a soft-core CPU and an OpenLane tape-out flow.

How every lesson works

Each lesson runs the same seven-part structure: learning material, active recall, conceptual questions, practice problems, a Feynman explanation, error analysis, and a mini challenge, then a quiz you have to pass to mark it complete. Completed modules enter a spaced-repetition queue that asks you real questions at 1, 3, 7, 14, 30 and 60 days, and reschedules from what you actually get right.

Full syllabus

• The C++ development environment (locked)
• C++ essentials & the memory model (locked)
• Operators & expressions (locked)
• Functions in C++ (locked)
• References & const-correctness (locked)
• Arrays (locked)
• Classes, RAII & pointers (locked)
• Constructors, encapsulation & composition (locked)
• Operator overloading (locked)
• STL: strings, maps & iterators (locked)
• Timing functions (locked)
• PROJECT: A PID golden reference model in C++ (locked)
• Serial communication in C++ (locked)
• Finite state machines in C++ (locked)
• PROJECT: Serial sensor reader (locked)
• PROJECT: Differential drive simulator (locked)
• Review & Retention // C++ for Robotics / Embedded (locked)
• Digital fundamentals: number systems & Boolean algebra (locked)
• HDL syntax & modules (locked)
• HDL mindset & combinational logic (locked)
• Sequential logic & testbenches (locked)
• Finite state machine design (locked)
• PROJECT: Traffic-light FSM in Verilog (locked)
• Simulation & synthesis (locked)
• PROJECT: Arithmetic logic unit (ALU) (locked)
• Review & Retention // VHDL / Verilog (locked)
• Semiconductors & the MOSFET switch (locked)
• What is VLSI? CMOS fundamentals (locked)
• PROJECT: Design & analyze a CMOS NAND gate (locked)
• Chip fabrication overview (locked)
• The chip design flow (RTL → GDSII) (locked)
• Standard cells & verification (locked)
• PROJECT: CMOS standard-cell gate library (locked)
• PROJECT: ASIC design exercise (RTL to layout) (locked)
• Review & Retention // VLSI (locked)
• Inheritance (locked)
• Polymorphism & abstract classes (locked)
• Copy semantics & the rule of five (locked)
• Smart pointers & resource management (locked)
• Templates, STL & move semantics (locked)
• Lambdas & function objects (locked)
• Error-handling strategies (locked)
• Memory optimization & profiling (locked)
• Concurrency & real-time safety (locked)
• Futures & async tasks (locked)
• PROJECT: Lock-free SPSC ring buffer (locked)
• Project: multi-threaded sensor system (locked)
• Design patterns for robotics (locked)
• Configuration systems (locked)
• Project: embedded communication framework (locked)
• Project: robotics middleware library (locked)
• LAB // Run your C++ on a microcontroller (or native) (locked)
• Review & Retention // C++ for Robotics / Embedded (locked)
• Pipelining & parameterized design (locked)
• Memories & FIFOs (locked)
• Timing, metastability & clock domains (locked)
• PROJECT: UART with CDC-safe FIFO (locked)
• FPGA design flow (locked)
• PROJECT: RISC processor (locked)
• PROJECT: FPGA-based robotics controller (locked)
• LAB // FPGA: simulate free, or a $5-15 board (locked)
• Review & Retention // VHDL / Verilog (locked)
• Transistor sizing, delay & noise margins (locked)
• Layout, parasitics & power (locked)
• PROJECT: SPICE analysis of an inverter chain (locked)
• Static timing analysis (locked)
• Physical design (floorplan, place & route, clock trees) (locked)
• Design for test (DFT) (locked)
• Low-power design (locked)
• PROJECT: Pipelined processor (VLSI implementation) (locked)
• PROJECT: Hardware accelerator for robotics (locked)
• LAB // SPICE + open silicon (free), TinyTapeout (locked)
• Review & Retention // VLSI (locked)
• P1 // Automated sorting/conveyor cell (PLC) (locked)
• P2 // Closed-loop PID process control + SCADA (locked)
• P3 // Networked embedded motor controller (the bridge) (locked)
• P4 // Integrated robot work-cell (the convergence) (locked)
• Hands-on // Git & GitHub (the universal signal layer) (locked)
• Hands-on // Portfolio & README craft (how to present your work) (locked)
• Hands-on // Interview prep (technical + behavioral) (locked)
• Hands-on // Networking & the job search (locked)
• CAPSTONE: Soft-core CPU on an FPGA (locked)
• CAPSTONE: RTL-to-GDSII with OpenLane (locked)
• TURN 2 // Final Mastery Assessment (locked)
• TURN 1 // Final Mastery Assessment (locked)

All four courses are $240 together, $60 less than buying them one by one.