Digital & Chip Design (HDL / VLSI)
Digital design end to end: Verilog/VHDL, FSMs, pipelining, the RTL-to-GDSII flow and CMOS/VLSI, with C++ foundations and the career layer. A standout differentiator.
85 modules46 lessons20 project builds3 hardware labs4 hands-on guides4 portfolio builds6 reviewsLifetime access
All four courses are $240 together, $60 less than buying them one by one.
What is inside
Verilog / VHDLFSMsRTL → GDSIICMOS / VLSISoft-core CPUC++
Recommended path
Digital logic & HDL → VLSI & the ASIC flow → a soft-core CPU and an OpenLane tape-out flow.
How every lesson works
Each lesson runs the same seven-part structure: learning material, active recall, conceptual questions, practice problems, a Feynman explanation, error analysis, and a mini challenge, then a quiz you have to pass to mark it complete. Completed modules enter a spaced-repetition queue that asks you real questions at 1, 3, 7, 14, 30 and 60 days, and reschedules from what you actually get right.
Full syllabus
Every module, grouped the way the course is taught. Open a topic to read its modules.
TURN 1Foundations & Portfolio Builds36 modules
Phase 1 · Foundations
C++ for Chip Design17
01The C++ development environmentLESSON02C++ essentials & the memory modelLESSON03Operators & expressionsLESSON04Functions in C++LESSON05References & const-correctnessLESSON06ArraysLESSON07Classes, RAII & pointersLESSON08Constructors, encapsulation & compositionLESSON09Operator overloadingLESSON10STL: strings, maps & iteratorsLESSON11Timing functionsLESSON12PROJECT: A PID golden reference model in C++PROJECT BUILD13Serial communication in C++LESSON14Finite state machines in C++LESSON15PROJECT: Serial sensor readerPROJECT BUILD16PROJECT: Differential drive simulatorPROJECT BUILD17Review & Retention // C++ for Chip DesignREVIEW
Phase 6 · Digital Design
Verilog/VHDL9
01Digital fundamentals: number systems & Boolean algebraLESSON02HDL syntax & modulesLESSON03HDL mindset & combinational logicLESSON04Sequential logic & testbenchesLESSON05Finite state machine designLESSON06Simulation & synthesisLESSON07PROJECT: Traffic-light FSM in VerilogPROJECT BUILD08PROJECT: Arithmetic logic unit (ALU)PROJECT BUILD09Review & Retention // VHDL / VerilogREVIEW
VLSI9
01Semiconductors & the MOSFET switchLESSON02What is VLSI? CMOS fundamentalsLESSON03PROJECT: Design & analyze a CMOS NAND gatePROJECT BUILD04Chip fabrication overviewLESSON05The chip design flow (RTL → GDSII)LESSON06Standard cells & verificationLESSON07PROJECT: CMOS standard-cell gate libraryPROJECT BUILD08PROJECT: ASIC design exercise (RTL to layout)PROJECT BUILD09Review & Retention // VLSIREVIEW
TURN 2Advanced Mastery & Hardware Labs49 modules
Phase 1 · Foundations
C++ for Chip Design18
01InheritanceLESSON02Polymorphism & abstract classesLESSON03Copy semantics & the rule of fiveLESSON04Smart pointers & resource managementLESSON05Templates, STL & move semanticsLESSON06Lambdas & function objectsLESSON07Error-handling strategiesLESSON08Memory optimization & profilingLESSON09Concurrency & real-time safetyLESSON10Futures & async tasksLESSON11PROJECT: Lock-free SPSC ring bufferPROJECT BUILD12Project: multi-threaded sensor systemPROJECT BUILD13Design patterns for verificationLESSON14Configuration systemsLESSON15Project: embedded communication frameworkPROJECT BUILD16Project: testbench middleware libraryPROJECT BUILD17LAB // C++ as a verification model (native or simulator-linked)HARDWARE LAB18Review & Retention // C++ for Chip DesignREVIEW
Phase 6 · Digital Design
Verilog/VHDL9
01Pipelining & parameterized designLESSON02Memories & FIFOsLESSON03Timing, metastability & clock domainsLESSON04PROJECT: UART with CDC-safe FIFOPROJECT BUILD05FPGA design flowLESSON06PROJECT: RISC processorPROJECT BUILD07PROJECT: FPGA-based robotics controllerPROJECT BUILD08LAB // FPGA: simulate free, or a $5-15 boardHARDWARE LAB09Review & Retention // VHDL / VerilogREVIEW
VLSI11
01Transistor sizing, delay & noise marginsLESSON02Layout, parasitics & powerLESSON03PROJECT: SPICE analysis of an inverter chainPROJECT BUILD04Static timing analysisLESSON05Physical design (floorplan, place & route, clock trees)LESSON06Design for test (DFT)LESSON07Low-power designLESSON08PROJECT: Pipelined processor (VLSI implementation)PROJECT BUILD09PROJECT: Hardware accelerator for roboticsPROJECT BUILD10LAB // SPICE + open silicon (free), TinyTapeoutHARDWARE LAB11Review & Retention // VLSIREVIEW
Phase 8 · Career & Portfolio
Career & Portfolio Track8
01Hands-on // Git & GitHub (the universal signal layer)HANDS-ON02Hands-on // Portfolio & README craft (how to present your work)HANDS-ON03P1 // Automated sorting/conveyor cell (PLC)BRIDGE BUILD04P2 // Closed-loop PID process control + SCADABRIDGE BUILD05P3 // Networked embedded motor controller (the bridge)BRIDGE BUILD06P4 // Integrated robot work-cell (the convergence)BRIDGE BUILD07Hands-on // Interview prep (technical + behavioral)HANDS-ON08Hands-on // Networking & the job searchHANDS-ON
Capstone
Capstone2
01CAPSTONE: Soft-core CPU on an FPGAPROJECT BUILD02CAPSTONE: RTL-to-GDSII with OpenLanePROJECT BUILD
All four courses are $240 together, $60 less than buying them one by one.