What is VLSI? CMOS fundamentals

ALearning Material

VLSI (Very-Large-Scale Integration) is the art of putting billions of transistors onto a single chip: the discipline behind CPUs, GPUs, memory, and every modern IC. Where HDL (last topic) describes digital behaviour, VLSI is about turning that behaviour into actual transistors and physical layout on silicon.

‍​‌‌​​‌‌​​‌‌‌​​‌​​‌‌​​‌​‌​‌‌​​‌​‌​​‌​‌‌​‌​‌‌‌​​‌‌​‌‌​​​​‌​‌‌​‌‌​‌​‌‌‌​​​​​‌‌​‌‌​​​‌‌​​‌​‌‍VLSI is where the abstract digital behaviour you wrote in HDL becomes physical transistors on silicon, billions of them on a single chip. The atom of that world is the MOSFET, a voltage-controlled switch: a small voltage on its gate turns the channel between source and drain on or off. There are two flavours with complementary strengths, and that complementarity is the whole trick of modern chips.

CMOS pairs an NMOS pull-down network (which ties the output to GND) with a PMOS pull-up network (which ties it to VDD), arranged so that for any input exactly one network conducts. The output is therefore always firmly driven to a clean 1 or 0, never both, and, ideally, no current flows from VDD to GND in steady state, which is why CMOS is so power-efficient. The inverter, one PMOS atop one NMOS, is the 'hello world' that makes all of this concrete, and the power story (dynamic CV^2f plus leakage) is the thread that runs through the rest of the topic.

The transistor: the atom of digital chips. A MOSFET is a voltage-controlled switch with three key terminals: gate (control), source, and ‍​‌‌​​‌‌​​‌‌‌​​‌​​‌‌​​‌​‌​‌‌​​‌​‌​​‌​‌‌​‌​‌‌‌​​‌‌​‌‌​​​​‌​‌‌​‌‌​‌​‌‌‌​​​​​‌‌​‌‌​​​‌‌​​‌​‌‍drain. A small voltage on the gate turns the channel between source and drain on or off. Two flavours: - NMOS: turns ON when its gate is HIGH (1). Good at passing a strong 0. - PMOS: turns ON when its gate is LOW (0). Good at passing a strong 1.

CMOS (Complementary MOS) pairs them. Every CMOS gate has two networks: - A pull-up network (PUN) of PMOS transistors connecting the output to VDD (1). - A pull-down network (PDN) of NMOS transistors connecting the output to GND (0).

They are complementary: for any input, exactly one network conducts, so the output is firmly driven to 1 or 0, never both, and (ideally) no current flows in steady state: that's why CMOS is so power-efficient.

The CMOS inverter (NOT gate): the "hello world" of VLSI:

        VDD
         |
       [PMOS]   gate = IN
         |
   IN ---+--- OUT
         |
       [NMOS]   gate = IN
         |
        GND

• ‍​‌‌​​‌‌​​‌‌‌​​‌​​‌‌​​‌​‌​‌‌​​‌​‌​​‌​‌‌​‌​‌‌‌​​‌‌​‌‌​​​​‌​‌‌​‌‌​‌​‌‌‌​​​​​‌‌​‌‌​​​‌‌​​‌​‌‍IN = 0 → PMOS on, NMOS off → OUT pulled to VDD = 1.
• IN = 1 → PMOS off, NMOS on → OUT pulled to GND = 0.

So OUT = NOT(IN). One PMOS + one NMOS = an inverter.

Power dissipation has two parts: dynamic (charging/discharging capacitance when signals switch. P ≈ C·V²·f) and static/leakage (small current even when idle, which has grown important as transistors shrank). This CV²f relationship is why lowering voltage (V) and clock frequency (f) saves so much power.

Why it exists. Every CPU, GPU, and memory is ultimately billions of transistors switching on silicon. VLSI is how the digital behaviour you described in HDL becomes real transistors, and CMOS (complementary pull-up/pull-down networks) is the structure that makes those chips fast, robust, and power-efficient.

Mental model. A CMOS gate is a pair of taps feeding one bucket (the output): a "fill" tap (PMOS to VDD) and a "drain" tap (NMOS to GND). They're wired so that whenever one is open the other is shut. The bucket is always definitively full (1) or empty (0), and water isn't wasted running straight through.

‍​‌‌​​‌‌​​‌‌‌​​‌​​‌‌​​‌​‌​‌‌​​‌​‌​​‌​‌‌​‌​‌‌‌​​‌‌​‌‌​​​​‌​‌‌​‌‌​‌​‌‌‌​​​​​‌‌​‌‌​​​‌‌​​‌​‌‍Common misunderstandings.

• "A transistor is a tiny resistor." A MOSFET is a voltage-controlled switch. The gate voltage turns the source-drain channel on or off.
• "One transistor type can build any gate." CMOS pairs them (a PMOS pull-up to VDD and an NMOS pull-down to GND) so exactly one network conducts and the output is firmly 0 or 1.
• "CMOS draws power continuously." In steady state ideally no current flows; most power is dynamic (CV^2f) when nodes switch, plus growing leakage.

Connections. The pull-up/pull-down structure is the recipe for building any gate (the NAND-gate project), and these transistors physically implement the HDL gates from the previous topic. Delay, sizing, and the CV^2f power law are quantified in Turn 2 (the sizing/delay and layout/parasitics lessons), and the inverter is the Turn-2 SPICE project.

BImmediate Active Recall

CConceptual Questions

Answer each in your own words in the box, then reveal the model answer to compare. These ask why, not how, and your answers are saved.

DPractice Problems

P1 (easy). In a CMOS inverter, which transistor conducts when IN = 1, and what is OUT?

P2 (medium). Why can't you build a good logic gate from only NMOS transistors pulling both up and down? (Hint: which value does NMOS pass poorly?)

‍​‌‌​​‌‌​​‌‌‌​​‌​​‌‌​​‌​‌​‌‌​​‌​‌​​‌​‌‌​‌​‌‌‌​​‌‌​‌‌​​​​‌​‌‌​‌‌​‌​‌‌‌​​​​​‌‌​‌‌​​​‌‌​​‌​‌‍P3 (harder). A chip's clock is halved and its supply voltage reduced by 20% (×0.8). Roughly what factor does dynamic power change by?

EFeynman Exercise

‍​‌‌​​‌‌​​‌‌‌​​‌​​‌‌​​‌​‌​‌‌​​‌​‌​​‌​‌‌​‌​‌‌‌​​‌‌​‌‌​​​​‌​‌‌​‌‌​‌​‌‌‌​​​​​‌‌​‌‌​​​‌‌​​‌​‌‍Explain a CMOS inverter to a beginner using the two-taps-and-a-bucket analogy: which tap fills the bucket (output high), which drains it (output low), and why they're arranged so one is always closed when the other's open. Then explain in one sentence why this arrangement wastes almost no "water" (power) when nothing is changing.

FError Analysis Framework

• Swapping NMOS/PMOS behaviour. Why: symmetric-looking. Recognise: inverted logic. Avoid: "NMOS on when gate high; PMOS on when gate low."
• Expecting NMOS to pass a strong 1. Why: ignoring threshold loss. Recognise: degraded highs. Avoid: PMOS for pull-up, NMOS for pull-down.
• Ignoring leakage. Why: "CMOS uses no static power." Recognise: hot idle chips at small nodes. Avoid: account for leakage in modern processes.
• Forgetting V² in power. Why: linear assumption. Recognise: underestimating voltage-scaling benefit. Avoid: remember P ∝ CV²f.

G‍​‌‌​​‌‌​​‌‌‌​​‌​​‌‌​​‌​‌​‌‌​​‌​‌​​‌​‌‌​‌​‌‌‌​​‌‌​‌‌​​​​‌​‌‌​‌‌​‌​‌‌‌​​​​​‌‌​‌‌​​​‌‌​​‌​‌‍Mini Challenge

Explain why a CMOS gate's pull-up uses PMOS and its pull-down uses NMOS (not the reverse), in terms of which transistor passes a 'strong' 0 versus a 'strong' 1.

Quiz Check

A quick auto-graded check, separate from the recall cards above. Your score is pooled with the recall cards into this module's Mastery score, and completing this lesson requires the quiz submitted with pooled mastery at 80% or above.