The chip design flow (RTL → GDSII)

ALearning Material

Designing a chip is a pipeline that turns behaviour into a manufacturable layout. Knowing the stages (and their jargon) is essential VLSI literacy.

Designing a chip is a pipeline that turns behaviour into a manufacturable layout, and knowing the stages and their jargon is basic VLSI literacy. It runs from specification, to RTL design in HDL, to functional verification, to logic synthesis (RTL becomes a gate-level netlist of standard cells), to physical design (place and route), to sign-off checks, and finally to GDSII, the layout file sent to the foundry at tape-out.

‍​‌‌​​‌‌​​‌‌‌​​‌​​‌‌​​‌​‌​‌‌​​‌​‌​​‌​‌‌​‌​‌‌‌​​‌‌​‌‌​​​​‌​‌‌​‌‌​‌​‌‌‌​​​​​‌‌​‌‌​​​‌‌​​‌​‌‍Two themes dominate. First, verification is often the majority of the work, because an ASIC bug can't be patched: finding it after fabrication means a costly, months-long re-spin, which is also the crux of the ASIC-versus-FPGA choice: an FPGA configures your RTL onto a reprogrammable chip (fast, cheap to iterate, lower performance), while an ASIC manufactures custom silicon (huge upfront cost, best performance at volume). Second, timing dominates sign-off: a synchronous chip only works if every signal meets setup and hold everywhere, which Static Timing Analysis checks exhaustively.

The flow, top to bottom:

1. Specification: what the chip must do (function, speed, power, area).
2. RTL design: describe behaviour in HDL (Verilog/VHDL) at the Register-Transfer Level: registers + the logic between them. (This is what you learned in the HDL topic.)
3. Functional verification: simulate the RTL against testbenches; prove it's logically correct before spending effort on physical design. Verification is often the majority of the work on real chips.
4. ‍​‌‌​​‌‌​​‌‌‌​​‌​​‌‌​​‌​‌​‌‌​​‌​‌​​‌​‌‌​‌​‌‌‌​​‌‌​‌‌​​​​‌​‌‌​‌‌​‌​‌‌‌​​​​​‌‌​‌‌​​​‌‌​​‌​‌‍Logic synthesis: a tool converts RTL into a gate-level netlist of standard cells (predefined AND/OR/flip-flop layouts) from a technology library, optimising for timing/area/power.
5. Physical design (place & route): arrange the cells on the die (placement) and connect them with metal wiring (routing), respecting design rules.
6. Sign-off checks: - STA (Static Timing Analysis): verifies the design meets timing at the target clock without exhaustive simulation (checks setup/hold across all paths). - DRC (Design Rule Check): geometry obeys the foundry's manufacturing rules. - LVS (Layout vs Schematic): the layout matches the intended netlist.
7. GDSII: the final layout file sent to the foundry ("tape-out") to make masks and fabricate the chip.

ASIC vs FPGA: two destinations for RTL: - FPGA: your RTL is configured onto a reprogrammable chip. Fast to iterate, cheaper upfront, lower performance/efficiency. Great for prototyping/low volume. - ‍​‌‌​​‌‌​​‌‌‌​​‌​​‌‌​​‌​‌​‌‌​​‌​‌​​‌​‌‌​‌​‌‌‌​​‌‌​‌‌​​​​‌​‌‌​‌‌​‌​‌‌‌​​​​​‌‌​‌‌​​​‌‌​​‌​‌‍ASIC: your RTL is manufactured into custom silicon. Huge upfront cost (masks, months), but best performance/power/cost at high volume. A mistake means a costly re-spin, hence heavy verification.

Why timing dominates. A synchronous chip works only if every signal arrives at its flip-flop within one clock period (setup) and not too early (hold). STA checks this everywhere. Missing timing = the chip won't run at its rated speed.

Why it exists. Turning chip behaviour into a manufacturable layout is a long pipeline, and a single mistake taped out to a foundry costs months and a fortune. Knowing the flow (RTL, verification, synthesis, place-and-route, signoff, GDSII) and its jargon is essential VLSI literacy and the map behind the OpenLane capstone.

Mental model. The flow is like publishing a book: spec = outline, RTL = manuscript, verification = editing/proofreading, synthesis = typesetting into standard fonts/ blocks, place & route = laying out pages and the index, sign-off = final print check, GDSII = the printing plates sent to the press. Once printed (taped out), fixing a typo means a whole new print run, so you proofread obsessively.

‍​‌‌​​‌‌​​‌‌‌​​‌​​‌‌​​‌​‌​‌‌​​‌​‌​​‌​‌‌​‌​‌‌‌​​‌‌​‌‌​​​​‌​‌‌​‌‌​‌​‌‌‌​​​​​‌‌​‌‌​​​‌‌​​‌​‌‍Common misunderstandings.

• "Synthesis or layout is the bulk of the work." Verification often dominates. You prove the RTL correct before physical design, because a fabricated bug means a costly re-spin.
• "FPGA and ASIC are the same target." FPGA configures reprogrammable hardware (fast, cheap to iterate); ASIC manufactures custom silicon (huge upfront cost, best performance at volume).
• "If it is logically correct it will run at speed." Timing dominates. STA must confirm every path meets setup/hold at the target clock, or the chip will not hit its rated frequency.

Connections. RTL is exactly the HDL you wrote (HDL topic), and STA/setup-hold is the timing lesson (HDL Turn 2) at signoff. This is the flow the OpenLane RTL-to-GDSII capstone walks end to end, and verify-before-committing mirrors simulate-before-you-cut in CNC and predict-then-measure in electronics.

BImmediate Active Recall

CConceptual Questions

Answer each in your own words in the box, then reveal the model answer to compare. These ask why, not how, and your answers are saved.

DPractice Problems

P1 (easy). Which stage turns your Verilog into specific AND/OR/flip-flop cells?

P2 (medium). Why is functional verification done ‍​‌‌​​‌‌​​‌‌‌​​‌​​‌‌​​‌​‌​‌‌​​‌​‌​​‌​‌‌​‌​‌‌‌​​‌‌​‌‌​​​​‌​‌‌​‌‌​‌​‌‌‌​​​​​‌‌​‌‌​​​‌‌​​‌​‌‍before synthesis and physical design, not after tape-out?

P3 (harder). A startup needs to iterate a design weekly during R&D, then ship millions of units. Which target for R&D, which for production, and why?

EFeynman Exercise

Explain the RTL-to-GDSII flow to a beginner using the book-publishing analogy. Match each stage (spec, RTL, verification, synthesis, place & route, sign-off, GDSII) to a publishing step. Then explain why "tape-out is like sending plates to the press". Why fixing a mistake afterward is so painful, and what that means for how much you verify.

FError Analysis Framework

• Skipping/under-verifying. Why: eager to tape out. Recognise: bugs found in silicon. Avoid: invest heavily in verification before synthesis.
• Confusing synthesis with place & route. ‍​‌‌​​‌‌​​‌‌‌​​‌​​‌‌​​‌​‌​‌‌​​‌​‌​​‌​‌‌​‌​‌‌‌​​‌‌​‌‌​​​​‌​‌‌​‌‌​‌​‌‌‌​​​​​‌‌​‌‌​​​‌‌​​‌​‌‍Why: both "tooling." Recognise: mixing logical vs physical stages. Avoid: synthesis = RTL→gates; P&R = gates→layout.
• Ignoring timing (STA). Why: focusing on function only. Recognise: chip fails at target clock. Avoid: meet setup/hold via STA sign-off.
• Wrong target (ASIC for prototyping). Why: not weighing iteration cost. Recognise: expensive, slow respins. Avoid: FPGA to iterate, ASIC for volume.

GMini Challenge

For the same Verilog RTL, when would you target an FPGA versus an ASIC, and why is heavy verification especially critical for the ASIC path?

Quiz Check

A quick auto-graded check, separate from the recall cards above. Your score is pooled with the recall cards into this module's Mastery score, and completing this lesson requires the quiz submitted with pooled mastery at 80% or above.