Portfolio outcome: a transistor-level design of a 2-input CMOS NAND gate: its schematic (PUN/PDN), a truth-table verification, and a short analysis of why NAND is the "universal gate." Optionally simulate in a free tool (Falstad's circuit sim or LTspice). Demonstrates you can reason at the transistor level, not just RTL.
AThe project
You'll go below HDL to build a gate from transistors, the core VLSI skill. The method generalises to any CMOS gate:
This project takes you below HDL to build a logic gate from individual transistors. The core skill that makes VLSI feel real rather than abstract. The beauty is that one recipe builds every static CMOS gate, so once you internalise it you can construct any gate on demand.
The recipe: build the pull-down network from NMOS to implement exactly the condition where the output is 0 (series NMOS = AND of inputs, parallel = OR), then build the pull-up network from PMOS as the dual of the pull-down (series and parallel swapped) to implement the output-is-1 condition, with one NMOS and one PMOS per input. Working a NAND through this (two NMOS in series, two PMOS in parallel, four transistors) and verifying it against a truth table cements both the procedure and why the dual structure guarantees the complementary, never-both behaviour of CMOS.
Formulas & method. A static CMOS gate is two dual networks, and the sizing follows from carrier mobility:
PDN (NMOS, to GND) conducts when the output should be 0
series NMOS = AND of inputs parallel NMOS = OR of inputs
PUN (PMOS, to VDD) the DUAL of the PDN: series <-> parallel swapped
conducts when the output should be 1
RULE exactly one network conducts at a time -> no static current path VDD to GND
that is why static CMOS burns power only when SWITCHING
TRANSISTORS 2 per input: one NMOS in the PDN, one PMOS in the PUN
SIZING holes are ~2-3x less mobile than electrons, so for equal rise and fall:
W_p ~ 2-3 x W_n
series devices are slower: widen them in proportion to how many are in series
The method is to write the pull-down condition from the truth table first, then derive the pull-up as its dual rather than designing it separately. The dual is what guarantees the two networks are never on together, which is the property the whole gate depends on.
The CMOS recipe (memorise: it builds every static gate):
Derive the gate rather than recalling it: pull-down from the truth table, pull-up as its dual, then size it. Each step has a check you can do on paper before any simulator is involved.
Take the rows where the output is 0 and express that condition in NMOS: inputs that must all be low together become series devices, inputs where any one suffices become parallel ones. The PDN is the network you design; everything else follows from it.
Check: for every input combination that should output 0, a conducting path exists from output to GND, and for every combination that should output 1, no such path exists.
Build the PUN by swapping series for parallel throughout the PDN, in PMOS to VDD. Deriving rather than designing it is what guarantees the two networks are exactly complementary, and complementary is the whole reason static CMOS draws no current when it is not switching.
Check: for every input combination, exactly one of the two networks conducts. If you find a combination where both conduct, you have a short from VDD to GND; if neither, the output floats.
Confirm you have exactly two transistors per input, one NMOS in the PDN, one PMOS in the PUN. Any other count means the dual is wrong or an input has been handled twice, and it is the fastest possible check on the whole structure.
Check: transistor count is exactly 2N for an N-input gate.
Widen the PMOS devices relative to the NMOS to compensate for the lower hole mobility, and widen devices in series in proportion to how many are stacked. Unsized, the gate's rising edge is two to three times slower than its falling one, which shows up as asymmetric delay in every path through it.
Check: your calculated rise and fall drive strengths are roughly equal, and the series stacks have been widened rather than left at minimum.
Walk every input combination on paper against the intended truth table, then simulate. Paper first: a simulator will faithfully show you the behaviour of a gate you designed wrongly, and the truth table is what tells you which one you have.
Check: the simulated output matches the truth table for all input combinations, and the rise and fall times are within a small factor of each other.
Portfolio presentation. Publish the sources plus the reports, not just the layout image. Show the schematic/layout, then the numbers that prove it works: the timing/area/power summary, and the DRC/LVS clean confirmation. Add a sentence naming the process/PDK and the tool flow (OpenLane, ngspice) so the result is reproducible. In silicon, the signoff reports are the portfolio.
For a 2-input NAND Y = NOT(A AND B) (Y=0 only when A=1 AND B=1):
- PDN: output goes low only when both A and B are 1 → two NMOS in series
between Y and GND.
- PUN (dual): two PMOS in parallel between VDD and Y.
Step: verify with the truth table (trace which network conducts):
| A | B | NMOS series (PDN)? | PMOS parallel (PUN)? | Y |
|---|---|---|---|---|
| 0 | 0 | off (both needed) | on (either A or B low) | 1 |
| 0 | 1 | off | on (A low) | 1 |
| 1 | 0 | off | on (B low) | 1 |
| 1 | 1 | on (both high) | off (both high) | 0 |
That's exactly NAND. 4 transistors total.
Step: analysis writeup: explain (1) why PUN is the dual of PDN, (2) that the gate draws ~no static current (one network always off), and (3) why NAND is universal (you can build NOT, AND, OR, hence any logic, from NANDs), which is why chips are often dominated by NAND-like cells.
Portfolio: the schematic, the completed truth table, transistor count, and the 3-point analysis. Optionally a simulator screenshot sweeping the inputs.
Full solutiontry the steps first - click to reveal
The reference design: the truth table, the pull-down network derived from it, the pull-up as its dual, the transistor count, the sizing arithmetic and the verification. Work the steps first; deriving the PUN rather than designing it is the habit this project exists to build.
The gate. Y = NOT(A AND (B OR C)), an AND-OR-INVERT, AOI21.
Step 1: the pull-down network, from the rows where Y = 0.
| A | B | C | B OR C | A AND (B OR C) | Y |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 |
Y = 0 exactly when A = 1 AND (B = 1 OR C = 1). That sentence IS the pull-down network,
read directly in NMOS:
AND -> devices in SERIES (both must conduct for the path to exist)
OR -> devices in PARALLEL (either one completes the path)
PDN: Y
|
[ A ] <- A in series...
|
+----+----+
| |
[ B ] [ C ] <- ...with B parallel C
| |
+----+----+
|
GND
THE NMOS NETWORK IS THE BOOLEAN EXPRESSION, LITERALLY. An NMOS conducts when its gate
is HIGH, so "A high AND (B high OR C high)" is A in series with (B parallel C), and there
is nothing to invent.
Step 2: the pull-up as the dual.
THE DUAL RULE: swap SERIES for PARALLEL throughout, in PMOS to VDD.
PDN: A series (B parallel C)
PUN: A parallel (B series C)
PUN: VDD
|
+----+----+
| |
[ A ] [ B ] <- A in PARALLEL with...
| |
| [ C ] <- ...B in SERIES with C
| |
+----+----+
|
Y
DERIVE IT, DO NOT DESIGN IT. The mechanical swap guarantees the two networks are never
conducting at the same time (which would be a short from VDD to GND) and never both off
at the same time (which would leave Y floating). Design the PUN by reasoning about when
Y should be high and you will eventually get a combination where both are on - and the
symptom is a gate that works logically while drawing milliamps of static current.
CHECK IT ON ONE ROW: A=1, B=0, C=1. PDN: A conducts, C conducts -> path to GND, Y = 0.
PUN: A is off (PMOS conducts on a LOW gate), and B is off -> no path to VDD. Exactly one
network conducts. Every row behaves the same way, by construction.
Step 3: the transistor count.
3 inputs -> 3 NMOS in the PDN + 3 PMOS in the PUN = 6 transistors.
TWO PER INPUT, ALWAYS, FOR ANY STATIC CMOS GATE. If your count differs, the dual was
built wrongly - most often by adding an inverter somewhere, which is a signal that the
network was designed rather than derived.
AND NOTE WHAT THIS BUYS: implementing the same function as NOT(A) OR NOT(B AND C) with
discrete gates would be an OR gate (6 transistors) plus a NAND (4) plus two inverters
(4) = 14 transistors, and three gate delays. The single AOI21 is 6 transistors and one
gate delay. That is why real standard-cell libraries are full of AOI and OAI cells:
complex CMOS gates are cheaper than the gates you would compose them from.
Step 4: sizing for equal rise and fall.
THE REFERENCE: a minimum inverter, Wn = 0.65 um, Wp = 1.30 um (the 2:1 mobility ratio).
Every gate is sized so its WORST-CASE path has the same drive as that inverter.
PULL-DOWN, worst case: A in series with ONE of B or C -> 2 devices in series
two NMOS in series have twice the resistance of one, so DOUBLE each:
A: Wn = 1.30 um B: Wn = 1.30 um C: Wn = 1.30 um
PULL-UP, worst case: B in series with C -> 2 devices in series
already 2x for mobility, now 2x again for the series stack:
B: Wp = 2.60 um C: Wp = 2.60 um
A is ALONE in its parallel branch, so it needs no series compensation:
A: Wp = 1.30 um
TOTAL DIFFUSION WIDTH: 3 x 1.30 + 2 x 2.60 + 1.30 = 10.4 um
THE RULE IN ONE SENTENCE: size each device so that the SLOWEST path through the network
has the same resistance as the reference inverter. Devices in series are widened in
proportion to how many are in series; devices in parallel are not widened at all,
because either one alone must do the job.
AND NOTE WHICH DEVICES GOT EXPENSIVE: the two PMOS in series, at 2.60 um each, because
PMOS are already 2x wide for mobility and now 2x again for the stack. That is the same
arithmetic that makes NOR gates expensive and NAND gates cheap, showing up in a
different gate.
Step 5: verification.
ON PAPER FIRST, all eight rows:
A B C | PDN conducting? | PUN conducting? | Y | matches?
0 0 0 | A off -> no | A on -> YES | 1 | yes
0 0 1 | A off -> no | A on -> YES | 1 | yes
0 1 0 | A off -> no | A on -> YES | 1 | yes
0 1 1 | A off -> no | A on -> YES | 1 | yes
1 0 0 | A on; B,C off -> | A off; B,C both LOW | 1 | yes
| n1 has no path | so both PMOS on -> | |
| to GND -> no | B series C -> YES | |
1 0 1 | A on, C on -> YES | A off; C high so | 0 | yes
| | PMOS C off -> no | |
1 1 0 | A on, B on -> YES | A off; B high so | 0 | yes
| | PMOS B off -> no | |
1 1 1 | A on, B on -> YES | A off; B,C both off | 0 | yes
EXACTLY ONE NETWORK CONDUCTS IN EVERY ROW. That is the property to check, and it is
worth doing by hand for all eight before touching a simulator.
THEN SIMULATE:
* aoi21.sp - the gate, its truth table, and the static-current check
.include "tech.lib"
VDD vdd 0 DC 1.8
* PDN: A in series with (B parallel C)
MNA y a n1 0 nch W=1.30u L=0.15u
MNB n1 b 0 0 nch W=1.30u L=0.15u
MNC n1 c 0 0 nch W=1.30u L=0.15u
* PUN: A in parallel with (B series C)
MPA y a vdd vdd pch W=1.30u L=0.15u
MPB n2 b vdd vdd pch W=2.60u L=0.15u
MPC y c n2 vdd pch W=2.60u L=0.15u
CL y 0 10f
VA a 0 PWL(0n 0 1n 0 1.1n 1.8 10n 1.8)
VB b 0 PWL(0n 0 3n 0 3.1n 1.8 10n 1.8)
VC c 0 PWL(0n 0 5n 0 5.1n 1.8 10n 1.8)
.measure tran idd_static AVG i(VDD) FROM=9n TO=10n
.tran 10p 10n
.end
PAPER BEFORE SIMULATION, AND THIS IS WHY: a simulator will faithfully report the
behaviour of the network you actually netlisted. If the PUN is wrong - both networks
conducting on some input - the waveform still shows plausible-looking logic levels,
because the two networks form a resistive divider and Y sits at some intermediate
voltage that the plot's autoscale makes look like a valid level.
THE MEASUREMENT THAT CATCHES IT IS THE STATIC CURRENT: `idd_static` must be leakage
only, picoamps to nanoamps. Microamps or milliamps means both networks are conducting
somewhere, and no amount of staring at the logic waveform will show you that.
Why it exists. RTL hides what a gate really is; building one from transistors (choosing the NMOS pull-down and its dual PMOS pull-up) is the core VLSI skill, and it generalises to any static gate. The NAND in particular is the universal gate every chip is ultimately built from.
Mental model. Building a CMOS gate is like wiring two complementary switch banks to one lamp: the NMOS bank closes a path to ground only for the input pattern that should output 0, and the PMOS bank is its mirror image, closing a path to power for every other pattern, so the lamp is always firmly on or off.
Common misunderstandings.
- "Design the pull-up and pull-down independently." The PUN is the dual of the PDN (series in one becomes parallel in the other) so they are derived together.
- "Series NMOS means OR." Series NMOS implements AND (all must conduct); parallel NMOS implements OR.
- "NAND is just one gate." NAND is universal. Any logic function can be built from NANDs alone, which is why it is the workhorse cell.
Connections. This applies the CMOS pull-up/pull-down structure from the CMOS-fundamentals lesson at the transistor level, below the HDL gates of the previous topic. The dual-network recipe is what standard cells contain (the Turn-2 layout-and-parasitics lesson), and the same inverter/NAND is characterized quantitatively in the Turn-2 SPICE project.
BImmediate Active Recall
QUERYFor a 2-input CMOS NAND, describe the PDN and PUN transistor arrangements.
REVEAL
PDN = two NMOS in series (to GND); PUN = two PMOS in parallel (to VDD). The PUN is the dual of the PDN.
QUERYHow many transistors does a 2-input CMOS NAND need?
REVEAL
Four, two NMOS (series) + two PMOS (parallel).
QUERYWhy is NAND called a "universal gate"?
REVEAL
Any Boolean function can be built entirely from NAND gates (NAND can make NOT, AND, OR), so NAND alone is sufficient to implement all logic.
CConceptual Questions
Answer each in your own words in the box, then reveal the model answer to compare. These ask why, not how, and your answers are saved.
Why is the pull-up network the 'dual' of the pull-down network (series and parallel swapped)?
REVEAL MODEL ANSWER
The pull-down (NMOS) network is built to conduct exactly when the output should be 0; the pull-up (PMOS) must conduct exactly when the output should be 1, i.e. precisely when the pull-down does not. By De Morgan duality, swapping series for parallel between the NMOS and PMOS networks makes them logical complements, so for any input exactly one network conducts. That's what enforces the clean, never-both CMOS output.
For a 2-input NAND, why is the pull-down two NMOS in series and the pull-up two PMOS in parallel?
REVEAL MODEL ANSWER
NAND outputs 0 only when both A and B are 1, so the pull-down must conduct only when both inputs are high, which is two NMOS in series (a series path = AND). The dual pull-up must conduct when either input is low, which is two PMOS in parallel (a parallel path = OR). Series-NMOS captures the 'both high' pull-down condition, and parallel-PMOS is its dual.
How many transistors does a 2-input CMOS NAND use, and what's the general rule?
REVEAL MODEL ANSWER
It uses four transistors. Two NMOS in the pull-down and two PMOS in the pull-up. The general rule for static CMOS is one NMOS and one PMOS per input, so an N-input gate uses 2N transistors.
DPractice Problems
P1 (easy). For a 2-input NOR gate, what are the PDN and PUN arrangements? (Hint: it's the dual situation of NAND.)
P2 (medium). Trace the NAND: with A=1, B=0, which network conducts and what is Y?
P3 (project extension). Build a NOT gate (inverter) using only a NAND. How do you wire the two inputs?
Solutionsclick to reveal
P1. NOR Y = NOT(A OR B), Y=0 when A or B is 1 → PDN: two NMOS in parallel
(to GND); PUN (dual): two PMOS in series (to VDD). Also 4 transistors.
P2. A=1, B=0: the series NMOS PDN needs both high to conduct. B=0 breaks it, so PDN is off. In the PUN, PMOS_B has a low gate (B=0) so it's on, pulling Y to VDD → Y = 1. Matches the truth table.
P3. Tie both NAND inputs together to the signal: NAND(A, A) = NOT(A AND A) =
NOT(A). Connecting A to both inputs makes the NAND behave as an inverter.
EFeynman Exercise
Explain to a beginner how four transistors make a NAND gate, using the "fill tap / drain tap" picture: the two drain taps (NMOS) are in series so the bucket only empties when both are open (both inputs 1), and the two fill taps (PMOS) are in parallel so either one keeps it full. Then explain why being able to build everything from NANDs is such a big deal for chips.
REVEAL MODEL ANSWER
Building a CMOS gate is like designing two opposite plumbing systems for a sink. First you lay the 'drain' pipes (the NMOS pull-down) so water escapes to the floor (output = 0) only under exactly the conditions you want. Pipes in a row mean all valves must open (AND), side-by-side pipes mean any one will do (OR). Then you build the 'fill' pipes (the PMOS pull-up) as the mirror image (wherever the drain had pipes in a row, the fill has them side by side) so the sink is always either filling or draining, never both at once.
FError Analysis Framework
- PUN not the dual of PDN. Why: copying series/parallel wrongly. Recognise: output contention or wrong logic. Avoid: swap series↔parallel between networks.
- Wrong network for the function. Why: mixing AND/OR with series/parallel. Recognise: truth table fails. Avoid: series=AND, parallel=OR (in the PDN).
- Miscounting transistors. Why: forgetting one per input per network. Recognise: incomplete gate. Avoid: each input → 1 NMOS + 1 PMOS.
- Assuming NAND≈AND. Why: name similarity. Recognise: inverted outputs. Avoid: NAND = NOT(AND); add/trace the inversion.
GMini Challenge
Design the transistor networks for a 2-input NOR gate (Y = NOT(A OR B)): describe the pull-down and pull-up networks (series vs parallel) and the transistor count.
REVEAL MODEL ANSWER
NOR outputs 0 when A OR B is 1, so the pull-down must conduct whenever either input is high -> two NMOS in parallel (a parallel path = OR). The dual pull-up must conduct only when both inputs are low -> two PMOS in series (a series path = AND). So PDN = 2 NMOS in parallel, PUN = 2 PMOS in series, for 4 transistors total (one NMOS and one PMOS per input), the dual arrangement of the NAND.
Quiz Check
A quick auto-graded check, separate from the recall cards above. Your score feeds the dashboard Mastery metric. On a project it is optional. Working through the build walkthrough in section A is what completes this module.