ALearning Material
Underneath all of VLSI (every chip, every logic gate) is a single physical device: the MOSFET transistor, built from semiconductor material, acting as a voltage-controlled switch. Understanding the semiconductor basics and how a MOSFET switches is the physical foundation of everything in chip design: it's why a transistor can be a switch, and switches are what we build all digital logic from.
From semiconductor material to a switch:
SEMICONDUCTOR BASICS:
- SILICON: a semiconductor (between conductor and insulator); DOPING adds impurities to make it
N-type (extra electrons) or P-type (holes) - controllable conductivity is the key
- junctions of N and P type create devices (diodes, transistors)
THE MOSFET (the transistor of all digital chips) - a voltage-controlled switch:
- terminals: GATE, SOURCE, DRAIN; the GATE VOLTAGE controls whether current flows source<->drain
- NMOS: gate HIGH -> ON (conducts); gate LOW -> OFF. PMOS: the opposite (gate LOW -> ON)
- it's a SWITCH controlled by voltage: a tiny gate (an insulated capacitor) turns the channel on/off
- CMOS = complementary NMOS + PMOS -> efficient digital logic (covered next/already)
The chain from material to logic. Silicon is a semiconductor, midway between a conductor and an insulator, and the key trick is doping: adding impurities makes N-type (extra free electrons) or P-type (holes: missing electrons) silicon, giving controllable conductivity. Putting N and P regions together creates devices. The MOSFET: the transistor every digital chip is built from: is a voltage-controlled switch with a gate, source, and drain: the voltage on the (insulated) gate controls whether current flows between source and drain (forming or removing a conducting channel). NMOS turns on with a high gate (off with low); PMOS is the opposite. So a MOSFET is fundamentally a switch you control with a voltage, and since digital logic is built from switches, the MOSFET is the atom of all chips (CMOS combines NMOS+PMOS for efficient logic). The disciplines: semiconductors get controllable conductivity via doping (N/P-type), and the MOSFET is a voltage-controlled switch (gate controls the source-drain channel; NMOS on-high, PMOS on-low): the physical device beneath all digital logic.
Formulas & method (building a CMOS gate, and sizing it). Every static CMOS gate is two networks that are logical complements of each other:
PULL-DOWN NETWORK (PDN), NMOS, connects the output to GROUND -> drives a 0
PULL-UP NETWORK (PUN), PMOS, connects the output to VDD -> drives a 1
AND in the PDN = transistors in SERIES OR in the PDN = transistors in PARALLEL
and the PUN is the DUAL: series becomes parallel and parallel becomes series.
The rule that must hold on EVERY input combination: exactly one network conducts.
Both conducting is a short from VDD to ground; neither is a floating output.
Transistor count = 2 per input for a simple gate (one NMOS, one PMOS each).
An inverter is one of each. A NAND2 has its two NMOS in series (pull down only when both inputs are high) and its two PMOS in parallel. A NOR2 is the mirror image. A compound gate such as is built in one gate by building the PDN directly from the expression (A and B in series, that pair in parallel with C) and taking the dual for the PUN, which is why compound gates exist: fewer transistors and one logic level instead of three.
Sizing, so every gate has the same drive as a reference inverter. A PMOS carries roughly half the current of an NMOS of the same width, because hole mobility is about half electron mobility, so an inverter is sized , .
Transistors in series share the voltage, so each must be wider to keep the same drive: devices in series means each of width (the resistances add). Transistors in parallel each carry the full worst-case load alone, so each stays at width (only one may be conducting).
| Gate | Pull-down network | Pull-up network | Total width |
|---|---|---|---|
| NAND2 | two NMOS in series: each | two PMOS in parallel: each | |
| NOR2 | two NMOS in parallel: each | two PMOS in series: each |
Which is why a standard-cell library is built around NAND rather than NOR: the series devices land in the fast NMOS network instead of the already-weak PMOS one, so a NAND is smaller, faster and lower capacitance for the same logical function.
Why it exists. All digital logic is built from switches, and the physical switch is the MOSFET, so understanding the semiconductor physics that makes a MOSFET work (doped silicon, the gate-controlled channel) is the foundation of VLSI: it explains why a transistor can switch under voltage control, which is the basis of every gate, every chip. Without this physical grounding, the rest of chip design floats on an unexplained device.
Mental model. A MOSFET is like a voltage-controlled water valve: the gate is the handle, but instead of a mechanical handle it's an electrical one. A voltage on the gate opens or closes the channel between source and drain (the pipe), letting current flow or not. And the 'pipe' is made of doped silicon whose conductivity we engineered. A tiny voltage controls a switch, and from billions of these tiny voltage-controlled switches, we build all of digital logic.
Common misunderstandings.
- "A transistor is fundamentally complicated/mysterious." At the digital level a MOSFET is simply a voltage-controlled switch: the gate voltage turns the source-drain channel on or off; that switch is all you need to build logic.
- "NMOS and PMOS switch the same way." They're complementary: NMOS conducts when the gate is HIGH (off when low); PMOS conducts when the gate is LOW (off when high). CMOS uses both together (which is why it's efficient).
- "Doping is a minor detail." Doping is the key. It gives silicon controllable conductivity (N-type/P-type), which is what makes semiconductor devices (and thus transistors and chips) possible at all.
Connections. The MOSFET switch is the physical device beneath the CMOS-fundamentals lesson and the NAND-gate project; its switching underlies the Turn-2 sizing/delay and layout/power lessons; the semiconductor physics is the same as the diodes/transistors in electronics (etech). Now at the chip level; and 'logic from voltage-controlled switches' is the bedrock the whole VLSI topic (and all of digital hardware) rests on.
BImmediate Active Recall
QUERYWhat is doping, and why is it the key to semiconductors?
REVEAL
Doping is adding impurities to silicon (a semiconductor) to make it N-type (extra free electrons) or P-type (holes: missing electrons). It's the key because it gives silicon controllable conductivity, you engineer regions to conduct in specific ways, and putting N and P regions together creates devices (diodes, transistors). Without doping, silicon's conductivity couldn't be controlled, and semiconductor devices (transistors, chips) wouldn't be possible.
QUERYWhat is a MOSFET, and how does it act as a switch?
REVEAL
The MOSFET is the transistor every digital chip is built from: a voltage-controlled switch with a gate, source, and drain. The voltage on the (insulated) gate controls whether a conducting channel forms between source and drain, i.e. whether current flows source<->drain. So a small gate voltage turns the switch on or off: it's a switch you control with a voltage, which is exactly what's needed to build digital logic (logic is built from switches).
QUERYHow do NMOS and PMOS differ?
REVEAL
They're complementary: an NMOS transistor conducts (is ON) when its gate is HIGH (and is OFF when the gate is low); a PMOS is the opposite. It conducts (is ON) when its gate is LOW (off when high). CMOS logic uses both together (complementary NMOS + PMOS), which is what makes it efficient (one type pulls the output high, the other pulls it low). So NMOS = on-with-high, PMOS = on-with-low.
QUERYWhy is the MOSFET the 'atom' of all digital chips?
REVEAL
Because all digital logic is built from switches, and the MOSFET is the physical switch, a tiny, voltage-controlled on/off device. Every logic gate is made of MOSFETs switching (CMOS combines NMOS+PMOS), and a chip is billions of these switches. So the MOSFET is the fundamental building block, the atom, from which all gates, and therefore all chips and all digital computation, are constructed. Understanding it physically grounds everything in VLSI.
CConceptual Questions
Answer each in your own words in the box, then reveal the model answer to compare. These ask why, not how, and your answers are saved.
Why is understanding the MOSFET as a voltage-controlled switch (and the semiconductor physics behind it) the essential physical foundation of VLSI, and how does it connect material physics to digital logic?
REVEAL MODEL ANSWER
Understanding the MOSFET as a voltage-controlled switch is the essential physical foundation of VLSI because it answers the most basic question the whole field rests on, what physical thing actually implements the switches that all digital logic is built from, and it connects, in one device, the material physics of semiconductors to the abstract world of logic gates and computation. Digital logic, at every level, is built from switches: a logic gate is switches arranged to produce an output from inputs, a chip is billions of gates, a computer is chips, so the entire edifice depends on having a tiny, fast, controllable, manufacturable switch, and the MOSFET is that switch. Grasping it as a voltage-controlled switch (a gate voltage turns the source-drain channel on or off) is what lets you understand everything above it: once you know the transistor is a switch you control with a voltage, you can understand how gates are built (arrangements of switches), how CMOS works (complementary switches pulling the output high or low), and ultimately how all digital hardware functions. It's the device that makes 'logic from switches' physically real. The semiconductor physics behind it explains why this switch is possible, which is the deeper foundation. Silicon is a semiconductor, neither a good conductor nor a good insulator, and the trick of doping (adding impurities to make N-type or P-type material) gives it controllable conductivity, which is exactly what you need to make a controllable switch. The MOSFET exploits this: an insulated gate over a doped-silicon channel, where the gate's voltage attracts or repels charge carriers to form or remove a conducting channel between source and drain, so a voltage (which costs almost no current, because the gate is insulated, like a capacitor) controls whether current flows. This is why the MOSFET is such a good digital switch: it's controlled by voltage (so one gate's output voltage can control the next, enabling logic to cascade), it draws negligible gate current (efficient), it's tiny, and it can be made by the billions. So the chain is: semiconductor physics (doped silicon with controllable conductivity) -> a voltage-controlled switch (the MOSFET) -> logic gates (switches arranged) -> chips (billions of gates) -> computation. Understanding the bottom of that chain (the physics and the switch) grounds the entire field, because without it the transistor is an unexplained black box and everything above floats on mystery. It connects material physics to digital logic by showing that the abstract 1s and 0s and gates of digital design are, physically, doped-silicon switches turning on and off under voltage control. That the logical and the physical are the same thing viewed at different levels. This is why every VLSI curriculum starts here: you must know what a transistor is (a voltage-controlled semiconductor switch) and why it works (doping gives controllable conductivity, the gate controls the channel) to truly understand chip design, because chip design is, at bottom, the art of arranging billions of these physical switches into computation. It's the bedrock that makes all the higher-level abstractions real and comprehensible.
Why is the complementary nature of NMOS and PMOS (one on with a high gate, the other with a low gate) so important, and how does it set up the efficiency of CMOS logic?
REVEAL MODEL ANSWER
The complementary nature of NMOS and PMOS is important because having two switch types that turn on under opposite gate conditions is exactly what enables CMOS, the logic style used in essentially all modern chips, to build gates that are both correct and remarkably efficient, with the complementary behavior being the very mechanism that delivers the efficiency. Recall the two devices: an NMOS transistor conducts when its gate is high (and is off when low), while a PMOS conducts when its gate is low (and is off when high). Mirror images of each other. This oppositeness is powerful because it means that for any given gate-input condition, you can arrange for one type to be on while the other is off, and vice versa for the opposite condition. CMOS exploits this by building each gate from two complementary networks: a pull-up network of PMOS transistors (which connect the output to the high supply) and a pull-down network of NMOS transistors (which connect the output to ground), arranged so that for any input combination, exactly one network conducts: the pull-up pulls the output high, or the pull-down pulls it low, but never both at once. This gives two properties. First, correct, full-swing logic: the output is always actively driven to a solid high or a solid low (via the conducting network), so the logic levels are clean and strong. Second (and this is the key efficiency) almost no static power consumption: because one network is always off whenever the other is on, there is no continuous conducting path from the supply to ground in steady state, so essentially no current flows except briefly during switching. A logic family that didn't have this complementary off/on arrangement (an older style with, say, a resistor pull-up) would have a constant current path in one of the output states, wasting power continuously; CMOS avoids this entirely because the complementary devices ensure one path is always broken. So the complementary NMOS/PMOS behavior isn't a curiosity. It's the foundation of CMOS's dominance: it lets you build every logic gate as complementary pull-up/pull-down networks that drive the output fully and burn almost no static power, which is why CMOS scales to billions of transistors on a chip without melting. This is why understanding that NMOS and PMOS switch oppositely matters at the device level: it's the physical basis for the efficient, full-swing, low-static-power logic that makes large-scale integration possible, and it sets up the entire CMOS methodology that the rest of VLSI builds on. The oppositeness of the two switches is, in a real sense, why modern chips can be as large and efficient as they are.
DPractice Problems
P1 (easy). Draw the CMOS transistor-level schematic for an inverter and a 2-input NAND, as a text description of each network: which transistors are in the pull-up network (PUN), which in the pull-down network (PDN), how they are connected, and the transistor count. Then fill in a table for the NAND with columns A, B, PDN conducting?, PUN conducting?, Y, and state the rule that must hold on every row.
P2 (medium). Design the CMOS gate for Y = NOT(A AND B OR C), the compound function usually called AOI21, directly as one gate. Give the PDN and PUN topologies and the transistor count. Then count the transistors and the logic levels you would need to build the same function out of a library AND2, OR2 and inverter, and say what the comparison tells you about why compound gates exist.
P3 (harder). Take an inverter sized with and as the reference drive strength. Size a NAND2 and a NOR2 so that each has the same worst-case drive as that inverter, in both directions. Give the width of every transistor and the total width of each gate. Then state which of the two gates a standard-cell library prefers and why, and why is twice in the first place.
Solutionsclick to reveal
P1. Inverter, 2 transistors.
- PUN: one PMOS, source to VDD, drain to the output, gate to A
- PDN: one NMOS, source to GND, drain to the output, gate to A
- A high turns the NMOS on and the PMOS off, pulling the output to GND. A low does the reverse.
2-input NAND, 4 transistors.
- PDN: two NMOS in series from the output down to GND, gates on A and B. Both must be on for the output to reach GND, which happens only when A and B are both high
- PUN: two PMOS in parallel from VDD to the output, gates on A and B. Either one being on pulls the output high, which happens when A or B is low
| A | B | PDN conducting? | PUN conducting? | Y |
|---|---|---|---|---|
| 0 | 0 | no (both NMOS off) | yes (both PMOS on) | 1 |
| 0 | 1 | no (A's NMOS off) | yes (A's PMOS on) | 1 |
| 1 | 0 | no (B's NMOS off) | yes (B's PMOS on) | 1 |
| 1 | 1 | yes (both on) | no (both PMOS off) | 0 |
The rule that must hold on every row: exactly one of the two networks conducts, never both and never neither.
Both conducting would be a direct path from VDD to GND, a short circuit drawing current continuously and producing an output somewhere in the middle that is neither a 0 nor a 1. Neither conducting would leave the output floating, driven by nothing, holding its last value on stray capacitance until it leaks away to an unpredictable level.
The structural guarantee that makes this always true is that the PUN and the PDN are logical duals: series in one is parallel in the other, on the same inputs, with complementary transistor types. That is not a convention, it is the reason static CMOS works, and it is why a static CMOS gate draws essentially no current at all when its inputs are steady. Current flows only during the brief moment of a transition when both networks are partly on. All of the dynamic power in the next lessons comes from that moment and from charging the load.
P2. Build the PDN from the expression as written. The PDN conducts when Y is low, which is when A AND B OR C is true:
- A in series with B (that is the AND)
- that pair in parallel with C (that is the OR)
- the whole network from the output down to GND
Three NMOS transistors.
Build the PUN as the dual. Swap every series for a parallel and every parallel for a series, with PMOS transistors:
- A in parallel with B
- that pair in series with C
- the whole network from VDD down to the output
Three PMOS transistors.
Total: 6 transistors, one logic level.
Check it on the row that matters. A = 1, B = 1, C = 0: the PDN's A-B series pair conducts, so Y is pulled low, correct. The PUN's C transistor has a low gate, so it is on, but the A-B parallel pair above it has both gates high, so both are off and the PUN is broken. Exactly one network conducts, as required.
The same function from library gates:
| Gate | Transistors | Why |
|---|---|---|
| AND2 | 6 | There is no such thing as a native CMOS AND: it is a NAND (4) followed by an inverter (2) |
| OR2 | 6 | Same: NOR (4) plus an inverter (2) |
| Inverter for the final NOT | 2 | |
| Total | 14 | three logic levels |
6 transistors and one level, against 14 and three.
Two things follow, and the second matters more.
Inverting gates are the primitives. NAND and NOR are cheap because their PDN and PUN come out of the duality directly. AND and OR are NAND and NOR with an inverter bolted on, so every non-inverting gate in a library costs an extra stage of delay and two extra transistors. This is why synthesised netlists are full of NAND, NOR and inverters and contain almost no AND or OR: the tool pushes the inversions around with De Morgan until they cancel.
Any function that can be written as one inverted sum-of-products can be one gate. The rule is mechanical: build the PDN from the uninverted expression, build the PUN as its dual, and you have a gate. That is where the whole AOI and OAI family in a standard-cell library comes from, and it is why a library has forty cells rather than five: each one is a common shape of logic collapsed into a single stage.
The limit is the next problem's subject. Stacking transistors in series makes the gate slower, so nobody builds a PDN four deep, and that is what stops the whole design from collapsing into one enormous gate.
P3. Why is twice . Both transistor types conduct by moving charge through a channel, but the carriers differ: NMOS conducts with electrons, PMOS with holes, and hole mobility in silicon is roughly half electron mobility. Two transistors of the same width therefore have roughly half the drive strength if they are PMOS. Making the PMOS about twice as wide equalises the pull-up and pull-down strength, which gives a symmetric output swing, equal rise and fall times, and a switching threshold near where the noise margins are balanced. The exact ratio is process-dependent and typically lands between 2 and 3.
Sizing rule. Transistors in series each carry the full current through the same path, so their resistances add: n in series need each to be n times wider to match a single one. Transistors in parallel are sized for the worst case, which is when only one of them is on, so each needs the same width as a single one.
NAND2. PDN is two NMOS in series, PUN is two PMOS in parallel.
| Transistor | Width | Why |
|---|---|---|
| NMOS A | 2 | Series pair: each doubled to match |
| NMOS B | 2 | |
| PMOS A | 2 | Parallel pair: worst case is one conducting alone, so each matches |
| PMOS B | 2 | |
| Total width | 8 |
NOR2. PUN is two PMOS in series, PDN is two NMOS in parallel.
| Transistor | Width | Why |
|---|---|---|
| NMOS A | 1 | Parallel pair: each matches |
| NMOS B | 1 | |
| PMOS A | 4 | Series pair of PMOS: doubled for the series stack on top of the already-doubled |
| PMOS B | 4 | |
| Total width | 10 |
(The reference inverter's total width is 3.)
The library prefers NAND. At equal drive, NOR2 is 25 percent larger than NAND2, and the gap widens fast with fan-in: a NAND3 totals 12 against a NOR3's 21, and a NOR4 would need 8-wide PMOS transistors that are both enormous and slow. Larger transistors also present a larger input capacitance, so a NOR gate loads whatever drives it more heavily, which slows the previous stage as well as itself.
The cause is the series stack landing on the weaker carrier. NAND puts its series stack in the NMOS network, where each transistor only has to be doubled from a width of 1. NOR puts its series stack in the PMOS network, where each transistor has to be doubled from a width that was already doubled for mobility. The penalty compounds.
This is why synthesis libraries carry NAND cells up to four or five inputs and NOR cells rarely past three, why a synthesised netlist is visibly NAND-heavy, and why the answer to "which gate should I write in RTL" is that it does not matter: the tool will rewrite your OR as a NAND of inverted inputs the moment it is cheaper, and it almost always is.
EFeynman Exercise
Explain to a beginner, using a voltage-controlled water valve made of specially-treated material: (1) why the gate is an electrical handle: a voltage opens or closes the channel between source and drain (letting current flow or not), (2) why the 'pipe' is doped silicon whose conductivity we engineered, and (3) why billions of these tiny voltage-controlled switches are what all digital logic is built from.
REVEAL MODEL ANSWER
A MOSFET transistor (the device every chip is built from) is best pictured as a voltage-controlled water valve made of specially-treated material. First, think of an ordinary valve with a handle that opens or closes a pipe; the MOSFET is like that, but its handle is electrical, not mechanical. The handle is called the gate, and instead of turning it by hand, you apply a voltage to it, and that voltage opens or closes the channel between the two ends (the source and the drain), deciding whether current flows through or not. A voltage on the gate, current flows (switch on); no voltage, no flow (switch off). A switch you control purely with a voltage. Second, the 'pipe' is made of doped silicon whose conductivity we engineered: silicon by itself is a so-so conductor (a 'semiconductor'), but by doping it, adding tiny amounts of impurities, we can make regions that conduct in just the way we want (N-type or P-type), and it's this engineered material that lets the gate's voltage form or remove the conducting channel. We literally tune the material so the switch works. Third (and this is the payoff) billions of these tiny voltage-controlled switches are what all digital logic is built from. A single switch isn't much, but digital logic (AND, OR, NOT, and everything built from them) is made of switches, and the MOSFET is the perfect tiny switch: controlled by a voltage (so one switch's output can flip the next), drawing almost no current at its gate (efficient), and small enough to pack billions onto a chip. So from one idea, a voltage-controlled valve made of engineered silicon, and an enormous number of them, you get every logic gate, every processor, every chip. That's the physical foundation of all of VLSI: the transistor is just a voltage-controlled switch, and switches are what we compute with.
FError Analysis Framework
- Thinking a transistor is fundamentally mysterious/complicated. Why: transistors seem complex. Recognise: at the digital level a MOSFET is just a voltage-controlled switch. Avoid: treat it as a switch: gate voltage turns the source-drain channel on/off.
- Assuming NMOS and PMOS switch the same way. Why: both are MOSFETs. Recognise: they're complementary, NMOS on-high, PMOS on-low. Avoid: remember NMOS conducts with a HIGH gate, PMOS with a LOW gate (CMOS uses both).
- Dismissing doping as a minor detail. Why: it's just adding impurities. Recognise: doping gives silicon controllable conductivity, the basis of all devices. Avoid: recognize doping (N/P-type) as the key that makes transistors/chips possible.
- Forgetting that all logic is built from these switches. Why: a transistor is one device. Recognise: you miss that gates/chips are billions of MOSFET switches. Avoid: see the MOSFET as the atom: switches -> gates -> chips -> computation.
GMini Challenge
Explain the semiconductor and MOSFET foundation for a VLSI beginner: semiconductors and doping (N/P-type), the MOSFET as a voltage-controlled switch (gate/source/drain, NMOS vs PMOS), why it's the atom of all chips, and how the complementary NMOS/PMOS sets up efficient CMOS logic.
REVEAL MODEL ANSWER
Semiconductors and doping: silicon is a semiconductor (between conductor and insulator). Doping adds impurities to make N-type (extra free electrons) or P-type (holes), giving controllable conductivity, and N/P regions together form devices. Doping is the key, without it, conductivity couldn't be controlled and transistors/chips wouldn't be possible.
The MOSFET (a voltage-controlled switch): the transistor every digital chip is built from, with a gate, source, and drain. The voltage on the insulated gate controls whether a conducting channel forms between source and drain (whether current flows). Because the gate is insulated (a capacitor), it draws negligible current, so one gate's output voltage can control the next (logic cascades). NMOS: ON when the gate is HIGH; PMOS: ON when the gate is LOW (complementary).
Why it's the atom of all chips: all digital logic is built from switches, and the MOSFET is the physical switch: tiny, voltage-controlled, efficient, mass-producible. Every gate is MOSFETs switching, and a chip is billions of them. So the chain is doped silicon -> a voltage-controlled switch (MOSFET) -> gates -> chips -> computation: understanding the bottom grounds the whole field (the abstract 1s/0s and gates are physically doped-silicon switches under voltage control).
How complementary NMOS/PMOS sets up efficient CMOS: because the two switch oppositely (NMOS on-high, PMOS on-low), CMOS builds each gate from a PMOS pull-up (to the high supply) and an NMOS pull-down (to ground), arranged so that for any input, exactly one network conducts, driving the output fully high or low, never both at once. This gives full-swing logic (clean, strong levels) and almost no static power (one network is always off, so no continuous supply-to-ground path. Current only flows briefly when switching). An older style (e.g. a resistor pull-up) would waste power continuously; CMOS avoids it because the complementary devices always break one path. So the oppositeness of NMOS/PMOS is the basis of CMOS's efficient, full-swing, low-static-power logic: why chips scale to billions of transistors without melting, and the foundation the rest of VLSI builds on (CMOS gates, the Turn-2 sizing/delay lesson and its layout/power lesson).
Quiz Check
A quick auto-graded check, separate from the recall cards above. Your score is pooled with the recall cards into this module's Mastery score, and completing this lesson requires the quiz submitted with pooled mastery at 80% or above.